Mentor Graphics' event U2U-2010 addresses
some of the key design issues in VLSI design
Mentor Graphics' annual User2User event held at Bangalore,
India was attended by 1000+ engineers, most of them were
young budding VLSI design professionals, some of them also
were engineering students from the colleges in Bangalore's
neighborhood. The event was both for semiconductor domain
as well as for embedded system professionals. The first
keynote was from one of the most popular electronics and
semiconductor industry expert Mr. Walden C Rhines, Chairman
and CEO of Mentor Graphics who listed 8 major issues/challenges
in VLSI design and fed the attendees with solutions.
The 8 issues/challenges he raised are low power design,
optimizing performance and power, exploding complexity in
functional verification, place and routing timing and power
closure issues, physical verification complexity, increasing
the manufacturing yield, reducing the cost of design, and
macro system integration.
His solutions include:
Holistic power approach: Apply power saving techniques at
every layer of design
Unified Power Format (UPF) compatible verification is one
of his suggestion.
ESL based design abstraction, smart comprehensive digital
verification flow which include intelligent tests, hardware-assisted
verification MCMM (multi-corner, multimode) for place and
route, multi-threading, integrating place and route with
physical verification.
But the major trend now in chip making is 3D chip stacking;
stacking chips one over the other and also one next to the
other. Here, Waden Rhines said its very challenging for
the tool developer in delivering tools for 3D chip stacking.
Mentor has some solution in its latest Calibre tool for
some of the listed challenges above.
To cut the chip design cost Walden's suggestion is to go
for embedded software automation and distributed model based
design.
He ended up with few praises for India semiconductor design
eco and the abundant fountain of talented engineers.
John Cooley of deepchip in his keynote speech has told
the VLSI designers to go more online (not social media like
twitter and facebook, but more of tech websites and forums)
to share the issues and solutions with peers, which may
benefit them to grow in their careers but warned about the
scary world of online techforums, where the fool and the
smart are easily identified.
Neeraj Paliwal of NXP Semiconductor suggested chip designers
to look IC design domain more at application point of view
rather than complex technology, In other words he was telling
to put a semiconductor chip wherever it can enhance the
life of people, i.e. every section of people. It can be
a chip on space shuttle to a chip on a bullock cart. The
four key design drivers in electronics as per him are energy
efficiency, connected mobile devices, security and health.
