Mentor Graphics partners EnSilica to develop
its FPGA IP platform
Mentor Graphics partners with EnSilica to develop its Precise-IP
vendor-independent FPGA IP platform. Thus EnSilica's range
of eSi-RISC embedded processor cores and eSi-Comms library
of communications IP that has been fully validated for use
in Mentor Graphics' Precision Synthesis FPGA design flow,
enabling design engineers to easily implement them on any
FPGA device.
"EnSilica provides a substantial catalogue of configurable
embedded processor cores and communications IP," said
Daniel Platzker, Product Line Director for FPGA synthesis
at Mentor Graphics. "By validating its IP for use with
Precision, EnSilica broadens the Precise-IP catalogue of
advanced partner cores, allowing our mutual customers to
benefit from Mentor Graphics' comprehensive, vendor-independent
FPGA design flow."
EnSilica's eSi-RISC is a family of configurable and low-power
soft processor cores for embedded systems that scales across
a wide range of applications. This processor architecture
is scalable from 16 bits to 32 bits and encompassing optional
DSP extensions, floating point and custom instructions.
The memory architecture can be configured for Harvard or
Von Neumann, or to include data and program caches. According
to EnSilica using a mix of 16-bit and 32-bit instructions
gives exceptional code density thus reducing the program
code size by up to 40% compared to leading FPGA vendor processors
such as NIOSII and MicroBlaze, while the minimum configuration
can be implemented in as little as 8K gates. System clock
speeds of over 200MHz can be achieved in Altera Stratix
IV and Xilinx Virtex-6 FPGAs and all processors use the
industry standard AMBA APB and AXI buses. EnSilica also
has a library of APB-based peripherals, including UART,
SPI, I2C, Timers and a 10/100 Ethernet MAC.
EnSilica's eSi-Comms library of communications IP is suitable
for many of the current air interface standards including
WLAN, WiMAX, DVB and DAB.
Precise-IP is Mentor Graphics' vendor-independent FPGA
IP platform. This platform includes RTL, physical and rad-tolerant
synthesis tools. The tool uses the same design source and
constraints to target all major device vendors, enabling
designers to synthesize eSi-RISC processors and eSi-Comms
IP for optimal performance on any FPGA technology.
"Our eSi-RISC embedded processor cores and eSi-Comms
IP library will give Mentor Graphics' Precision Synthesis
users an additional, distinctive edge to their FPGA designs,"
said Ian Lankshear, Managing Director of EnSilica. "Silicon-proven,
eSi-RISC's single architecture is scalable over a range
of embedded applications enabling companies to secure their
software investment while addressing a wide range of needs.
A high level of configurability enables hardware resources
to be optimised to application requirements, minimising
area and power to a level not possible with a general purpose
processor architecture. The highly pipelined nature of the
design gives customers a solution that can be easily migrated
between FPGA types or even to ASIC technologies."
All the eSi-RISC embedded processor cores and eSi-Comms
communications IP are available direct from EnSilica.
For more information visit: http://www.ensilica.com
