Debug platform for SoC verification jointly by Mentor and Lauterbach

Mentor Graphics and Lauterbach have collaborated to deliver a hardware-accelerated, software-development and debug platform for the verification of Systems-on-Chip (SoCs) and embedded systems.

The combined tool- setup, which includes Mentor's Veloce hardware emulation technology and Lauterbach's integrated debug and development tools handle concurrent hardware-software verification of embedded systems.

"As the market leader in the development and delivery of integrated software environments for embedded system applications, Lauterbach is committed to providing the best possible verification solutions for our customers. By combining with Mentor and their Veloce emulator, we can show our customers a high-speed platform that allows them to perform concurrent hardware-software integration many weeks or months before they are committed to real silicon, increasing their verification productivity and improving their time-to-market," said Norbert Weiss, International Sales & Marketing Manager, Lauterbach GmbH. "Our customers can now access a virtual hardware environment, that mimics the functionality of their real silicon, to debug their software at high-speeds using our standard toolsets."

"We worked closely with Lauterbach to implement this high-performance solution for embedded software debug." said Jim Kenney, Mentor Emulation Division (MED) director of marketing. "By teaming with Lauterbach we've ensured a solid software debug environment for our joint customers so they effectively validate the hardware-software interface of their System-on-Chip."