Interoperable EDA formats from TSMC for latest nodes

Taiwan Semiconductor Manufacturing Company (TSMC) has made available some of the unified and interoperable electronic design automation (EDA) technology files for its 65 nanometer (nm), 40nm and 28nm process nodes. The design technology file suite includes interoperable process design kit (iPDK), interoperable design rule check (iDRC), layout-versus-schematic (iLVS), and interoperable interconnect extraction (iRCX).

The iPDK, iDRC, iLVS, and iRCX technologies are developed and jointly validated with TSMC's EDA partners such as Mentor Graphics, Synopsys, Magma, Cadence, Ciranova and Springsoft under the industry-wide Interoperability Project.

"TSMC collaborates with multiple EDA vendors to create and validate interoperable EDA formats that accelerate data delivery and ensure the integrity and accuracy of advanced process technology data," said ST Juang, senior director of Design Infrastructure Marketing at TSMC, ", The latest version of the iPDK, iDRC, iLVS, and iRCX technology files are production design ready and incorporating the valuable feedback we received from customers and ecosystem partners during the beta test period. The new unified EDA data format provides designers the ability to select qualified EDA tools that match their design needs, improve compliance with TSMC processes, and ensure design accuracy for first-time silicon success."

The TSMC 65nm iPDK is available now. The 40nm iPDK, 65nm and 40nm iDRC and iLVS, and 28nm iRCX files are expected to be available in the second quarter of 2010. Technology files and the interoperable EDA format tool qualification results can be accessed at the TSMC Online customer design portal http://online.tsmc.com/online/ or by contacting TSMC account management and support executives for details.