Synopsys DDR memory IP supports Six DDR Standards in single PHY

Synopsys, provider of both IP and VLSI design software has made its new IP core DesignWare DDR multiPHY to support six DDR SDRAM standards, which include LPDDR2, LPDDR/Mobile DDR, DDR3, DDR3L (1.35 V), DDR3U (1.2x V), and DDR2. This IP allows VLSI designers to have their chip access any of these six DDR standards from single PHY for broad range of applications. The DesignWare DDR multiPHY supports data rates from 0 to 1066 Mbps and offers a DFI 2.1 compliant interface to the memory controller.

"Memory interfaces continue to be one of the key IP requirements we see in chip development. New standards such as DDR3, DDR3L and LPDDR2 are designed to meet system performance requirements while utilizing less power," said Dr. Keh-Ching Huang, Head of Marketing and IP Solution Planning at Global Unichip. "By supporting all facets of the DDR standards, Synopsys' unique DesignWare DDR multiPHY enables us to quickly incorporate the necessary functionalities into our SoC designs with less risk."

The DesignWare DDR multiPHY features include Delay Lock Loop (DLL) bypass modes for operation below 200 MHz, I/O retention mode to allow the chip's power supplies to be shut down completely while a small number of I/Os remain powered on to keep the external SDRAMs in self refresh mode. This IP is ready to support the anticipated DDR3U standard operating at 1.2 or 1.25 V. Additionally, the DesignWare DDR multiPHY provides built-in data training circuits to enable in-system calibration, providing optimized system-level timing without material interaction with the memory controller.

"It has become as important to minimize power as it has to minimize overall chip cost in portable electronics," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "The DesignWare DDR multiPHY not only offers designers the flexibility to utilize any DDR SDRAM in the system through simple software control, it also features a power-conscious design that minimizes the silicon area and cost."

To know more visit www.synopsys.com