Mentor Graphics and ST join hands to design chips down to 20nm nodes

Chipmaker ST Microelectronics and EDA tool specialist Mentor Graphics are collaborating to design and develop semiconductor chips at 32nm node and going further deep into 20nm technology nodes.

The Joint development named DeCADE to focus on developing EDA design tools and finally the SoC chips with analog and mixed signal functions. DeCADE solutions are for both core CMOS technologies and its derivatives technologies such as RF (Radio Frequency) and wireless technologies, and 3D Packaging and chip stacking technologies.

"This joint development effort will provide ST with tools to develop state-of-the-art Systems-on-Chips (SoCs) at 32-nm and below for ST's customers, taking full advantage of the strong Silicon Process, Device Modeling and Design know-how present on the Crolles Site," said Philippe Magarshack, STMicroelectronics General Manager of Central CAD & Design Solutions. "This ST-Mentor Graphics joint effort further reinforces the Crolles cooperative R&D cluster, which already gathers partners that develop and enable low-power SoCs and value-added application-specific technologies and is a great example of a project developed within the framework of the Nano2012 program."

"As a leading provider of semiconductor based solutions, ST is an excellent partner with whom to explore and develop the design methodologies that the market will need over the next decade," said Gregory K. Hinckley, President of Mentor Graphics. "We look forward to this collaboration as a further extension of Mentor Graphics efforts with our long term customer ST."