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   Date: 18th Feb 2010

Continuous Computing, picoChip and Cavium partnering on LTE femtocell reference design

Continuous Computing, picoChip and Cavium Networks have collaborated to deliver a complete Long Term Evolution (LTE) femtocell reference design that packs a LTE modem (PHY), radio frequency (RF) and packet processors, protocol software, intelligent router functionality and a complete Evolved Packet Core (EPC) simulator.

The LTE femtocell reference design consists of a microTCA system including a chassis with a picoChip modem, mezzanine RF card and Layer 1 physical layer (PHY) software, together with Cavium Networks' OCTEON Plus multi-core MIPS64 processor. Continuous Computing provides Trillium LTE Layer 2/3 protocols, the eNodeB reference application and a complete EPC Core Network Emulator (CNE). Continuous Computing's Trillium LTE eNodeB protocols have been optimized on Cavium's Simple Executive software environment to provide high performance and reduced latency.

"It is only with femtocells that LTE can truly meet its potential. They are the key to providing the experience that users will expect at a price that operators can afford. We believe that LTE femtocells ultimately will carry the vast majority of indoor mobile data traffic while also providing vital improvements to outdoor coverage and capacity, in both major cities and in remote areas," said Nigel Toon, CEO and President, picoChip. "While there are numerous vendor demonstrations of a subset of the functions of an LTE femtocell, this reference design represents the world's first integrated and fully-tested solution."

"The demand for LTE femtocells is unquestionable. We are already seeing operators asking for small cell access points to start testing in the second half of this year. Femtocells represent the key to avoiding the difficulties surrounding the first 3G deployments where rollouts cost too much, took too long and did not meet user expectations," said Mike Dagenais, President and CEO, Continuous Computing. "This LTE femtocell reference design is the culmination of a major three-way effort and represents highly sophisticated, state-of-the-art engineering and integration."

For more details visit www.ccpu.com, www.picochip.com, www.caviumnetworks.com


          
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