New innovations to improve density and I/O performance of Altera's 28-nm FPGAs

Altera has unveiled its new Embedded HardCopy Blocks method for partial reconfiguration and embedded 28-Gbps transceivers, which improves the density and I/O performance of Altera 28-nm FPGAs.

The Embedded HardCopy Blocks are customizable hard intellectual property (IP) blocks that leverage Altera's unique HardCopy ASIC capabilities. They are used to harden standard or logic-intensive functions such as interface protocols, application-specific functions, and custom IP.

Partial reconfiguration is to reconfigure part of the FPGA while other sections remain running, where uptime is critical because to make updates or adjust functionality without disrupting services. Lowering power and cost, partial reconfiguration also improves effective logic density by removing the necessity to place in the FPGA functions that do not operate simultaneously. Instead, these functions can be stored in external memory and loaded as needed. This reduces the size of the FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power.

The 28-Gbps embedded transceivers will implement designs such as 400G systems on a single chip without the need for costly external components.

Altera says, it is simplifying the partial reconfiguration process by building the capability on top of the incremental compile design flow in its Quartus II design software.

"Two years ago, Altera introduced the industry's first 40-nm FPGAs, and continued delivering industry firsts such as embedded 11.3-Gbps transceivers," said John Daane, president, chairman and CEO of Altera. "As we move to the next process node, these new innovations from Altera will take the industry beyond the benefits of Moore's Law to solve bandwidth challenges while staying within cost and power requirements."

For more details visit www.altera.com