Toshiba uses Synopsys' low power verification methodology to verify its chip designs

Toshiba Information Systems (Japan) uses Synopsys' voltage-aware VCS functional verification solution with MVSIM and Verification Methodology Manual for Low Power (VMM-LP) to deploy a uniform, structured and repeatable verification methodology to verify its low power chip designs.

Leveraging the documented methodology in the VMM-LP book and using the low power base classes, Toshiba Information Systems (Japan) was successful in verifying the low power functionality of a mobile multimedia application and setting up a testbench infrastructure that can be quickly adapted to other low power chip designs.

The methodology addresses all aspects of functional verification of power management functions, including suggestions for static versus dynamic verification, design-for-verification techniques, and use of assertions and coverage metrics to achieve verification closure. VMM-LP also defines SystemVerilog base classes that are power aware and enable setup of a reusable testbench.

"We are seeing a rapid increase in the complexity of low power designs in Japan," said Tomoji Takada, general manager, LSI Solutions Division, Toshiba Information Systems (Japan). "In addition to using a voltage-aware verification solution provided by VCS with MVSIM, we needed a structured methodology to enable efficient low-power verification and ensure high-quality designs. VMM-LP provided us this structured methodology. It also helped us to find ways to leverage our verification setup and build upon our verification expertise in OCP and AMBA-based environments and extend it from one low power project to the next."

"VMM-LP addresses the market need for innovation in low power verification," said Manoj Gandhi, senior vice president and general manager, Verification Group, Synopsys, Inc. "Our collaboration with Toshiba Information Systems (Japan) will help to deploy the VMM-LP methodology on many design projects. Synopsys will continue to invest and collaborate with industry leaders in developing and enabling next-generation verification methodologies."