Toshiba to expand use of Cadence tools for SoC design

Toshiba to use more EDA tools from Cadence in developing SoCs for mobile and consumer applications. The chip design tools from Cadence employed by Toshiba include Cadence Chip Planning system for chip planning of Toshiba SoC designs, DRC/LVS/ERC using the Cadence Physical Verification System, and acceleration of mixed signal design simulations with parallel processing utilizing Cadence Virtuoso Advanced Parallel Simulator.

"Cadence has worked with us across multiple design generations," said Tatsuo Noguchi, Technology Executive for SoC of Toshiba Corporation Semiconductor Company. "Integration of the Virtuoso custom IC design environment with the Encounter Digital Implementation System provides a significant flow and methodology advantage for hierarchical A/D floor planning, routing, electrical analysis, ECOs, and final chip finishing. The knowledge base we've established with Cadence throughout this long relationship will help us as we develop new and advanced designs."

"Cadence has been providing memory and discrete design solutions, including circuit simulation and Virtuoso custom design technologies to Toshiba designers for more than fifteen years," said Charlie Huang, senior vice president and chief strategy officer at Cadence. "The depth and breadth of this relationship, supported by our tireless investment in research and development, uniquely position our two companies and highlight the accomplishments we will achieve together. We are proud of our long-standing relationship with Toshiba and already working with their engineering teams to develop the next generation solutions that will keep them at the forefront of design."

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