Cadence and ARM joining hands to develop SoC design flow

Cadence and ARM collaborates to develop the System on Chip (SoC) design flow, accelerating and lowering the cost of SoC integration and verification.

Under the terms of the agreement, the Cadence Chip Planning System and Cadence Incisive Functional Verification solutions will be combined with ARM AMBA designer, Performance Exploration tools and Network Interconnect IP.

"Both ARM and Cadence have developed techniques to give our customers better methods to optimize SoC integration architectures and IP selection, and provide Verification IP (VIP)-based automation to speed both performance and functional verification time," said Steve Glaser, corporate vice president, Strategy and Planning at Cadence Design Systems. "With the evolution of ever more complex multimedia and multiprocessor SoC, there is a compelling need to find new ways to specify, optimize and verify both the performance and functionality of the SoC interconnect and the full SoC assembly."

"ARM and Cadence expect our customers to achieve major efficiency savings through the integration of both AMBA system IP and associated Cadence and AMBA design tools," said Michael Dimelow, director of marketing, ARM. "Early estimation of the power and cost of selected IP components enables customers to perform 'what if' calculations to optimize their SoC architectures. Generated traffic profiles from the AMBA Verification Performance Evaluation (VPE) tool rapidly tune the AMBA network interconnect performance, and Cadence metric-driven VIP ensures functional integrity of the integrated IP at SoC level."

The companies plan to deliver increasingly integrated solutions to joint customers in multiple phases through 2010.