Cray selects Gennum's Snowbush PCIe 3.0 PHY IP for its supercomputer design

Cray has selected Gennum's Snowbush PCIe 3.0 PHY IP for its high performance supercomputer design.

The Snowbush PCIe 3.0 IP PHY features a low power 5-tap Decision Feedback Equalization (DFE) and a high-performance H-bridge transmit driver. The PHY silicon footprint is small and includes the I/Os, ESD structures, and PCS Layer, in 1-, 2-, 3-, and 4-lane configurations to reduce silicon cost. Each lane of the PHY can be configured to operate in Gen 1, Gen 2, or Gen 3 mode. The multiple 4-lane PHYs can be configured as x8, x16, x32, and greater links. An on-chip Fractional-N PLL frequency synthesizer with integrated Spread Spectrum Clocking is used for simplified external clocking and reduced SoC complexity.

"After an extensive evaluation of competitive solutions, we selected Snowbush's high speed PCIe 3.0 PHY IP because it is the best solution available in the market today. Snowbush's reputation for high quality, reliable first-pass silicon offered our designers confidence that incorporating this IP block into our newest supercomputer design will give us a competitive edge in the market place," said Peg Williams, Senior Vice President of Research and Development at Cray.

The Snowbush PCIe PHY initially launched in June 2009, satisfies the 8 GT/s speed requirement of PCIe 3.0, and exceeds the anticipated critical specifications for jitter performance over harsh channels.

"Being the first to market with reliable first pass PCIe 3.0 IP silicon, is critical to ensuring that our customers get their new designs to market faster. Our leadership in developing serial-link IP at speeds of 5G or greater is encouraging Tier 1 customers, such as Cray, to adopt the IP and take advantage of this higher speed technology as they develop next generation interconnect solutions into their new designs," said Ewald Liess, General Manager of the Snowbush IP group for Gennum.

For more information visit www.gennum.com