Researchers getting closer to integrating
nanowires on CMOS semiconductor chips
Present CMOS chip fabrication process can go further down,
may be to 10 nm. Even to reach that stage the cost of fab
equipment will sky rocket. The best way to go further down
is to deviate from optolith process to self aligning nano
elements called nanowires or nanotubes. Semiconductor industry
is not ready to abruptly dump the litho based equipment
for nanowire based process due to cost and strategic reasons.
Researchers are working out a smooth transition from the
present CMOS to nano-element based by initially combining
both methods and use much of the present technologies for
some time atleast in moving over to a totally different
Silicon, being abundant and most affordable metal will
stay during the transition. So the challenge for the nano-technology
researchers is to commercialize their Nano technology idea
by effectively using present CMOS process, Silicon and its
Few breakthrough in this direction from researchers around
the world were noticed:
France based nano technology researcher Leti got step closer
to integrating Silcon nanowires into traditional CMOS semiconductor
chip making process.
Leti researchers have created silicon nanowire at temperature
of 400 Deg C by using a copper-based catalyst using a method
different from normal. The highlight of the research is,
they could generate nano devices at low temp of 400 Deg
C which is far less than what others are achieved. Most
of Silicon based nanowires were made in the temperature
of 600 Deg C to 1000 Deg C inside a furnace. Another highlight
is, researchers have created nanowires on oxidized metals.
Achieving at temperature convenient for making CMOS semiconductor
chips and on oxide material brings Leti close to integrating
nanowires on CMOS semiconductor chip. This way future System-on-Chip
(SoC) can house sensors and other nanotechnology based components
mainly the Optoelectronic devices. Well getting close to
Product on a Chip.
Leti researchers have published a article in Nature Nanotechnology
magazine, To view the article visit, http://www.nature.com/nnano/journal/vaop/ncurrent/abs/nnano.2009.234.html
University of California, Berkeley has put on its website
a report of its research work of growing Au-catalyzed vapor-liquid-solid
nanowire via metal-organic chemical vapor deposition. It
state "The nanoneedles grow on GaAs, silicon and sapphire
substrates and exhibit bright room-temperature photoluminescence.
The growths are conducted at 380 to 420 °C, making the
process ideal for silicon-CMOS integration". Visit
this link for more details http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-100.html
In another development researchers at Stanford University
have developed method of stacking and crystalline semiconductor
layers that sets the potential for three-dimensional microchips.
For details visit http://news.stanford.edu/news/2009/august24/crystal-nanowires-research-082609.html
Where is the immediate application of nanowire integrated
Due to their high surface-to-volume ratio, nanowires are
highly suitable for the electrical detection of chemical
or biological substances, converting solar to electrical
energy and in developing high energy storing batteries.
The immediate applications of nanowire integrated CMOS
chips are in health, environment and solar energy conversion.
Lab-on-chips have huge potential in providing better health
to bio on earth. Also energy generation will become far