Accellera approves an interoperability guide helping design re-use of IP components

Accellera, has approved the Accellera Verification Intellectual Property (VIP) Best Practices Interoperability Guide, a document resulting from the work of its VIP Technical Subcommittee (TSC), which was formed in May.

The Guide details how to use VIP components developed using SystemVerilog testbench environments based on either the Open Verification Methodology (OVM) or Verification Methodology Manual (VMM) interchangeably to lower verification costs and improve design quality.

"The results of Accellera's VIP Interoperability standardization effort makes it easier to reuse verification components and reduces the cost of repurchasing and rewriting IP for each new project or electronic design automation tool," said Shrenik Mehta, Accellera chair. "We applaud the efforts of Accellera's VIP TSC for reaching this significant milestone and for making their Best Practices Interoperability Guide available to the EDA community."

What's New in this guide?

The VIP Best Practices Interoperability Guide includes a VIP reference library that can be used as part of a verification interoperability methodology and a chapter devoted to introducing the high-level concepts of interoperability and component integration. It outlines a process that can be used to define a verification environment and select which cross-referenced best-practice sub-chapter or sub-chapters apply to specific integration challenges.

Accellera said its VIP TSC will continue its efforts to develop a Common Base Class Library (CBCL) and associated verification methodology with the goal of achieving IEEE standardization

To contribute and join Accellera's VIP TSC visit www.accellera.org/activities/vip

Why Interoperable VIP Components?
Verification solutions are ubiquitous, differing from company to company and among separate organizations within companies. Commercial tool suppliers do not support all the verification solutions in use today. The result is that there are many different methods for doing the same thing, requiring retraining and conversion costs. Interoperable VIP components reduce the cost of using and re-using VIP and improve the quality of design verification by eliminating translation errors.

For details visit www.accellera.com