TSMC characterizing its sub-40nm memory IP with Synopsys HSIM simulator

TSMC has adopted Synopsys' HSIM hierarchical FastSPICE circuit simulator for its sub-40-nanometer (nm) memory intellectual property (IP) characterization flow. The HSIM simulator will be deployed for TSMC advanced SRAM compilers for timing, power simulation, dynamic IR drop and EM analysis, and for full-chip simulation with extracted package models.

HSIM provides a comprehensive solution for circuit simulation, post-layout analysis, reliability analysis and electrical rule checking.

"At 40-nanometer nodes and beyond, post-layout parasitic data, power reliability and leakage need to be accounted for when characterizing memories," said ST Juang, senior director of Design Infrastructure Marketing at TSMC. "We had adopted HSIM for our memory IP characterization at previous technology nodes, and after extensive evaluation we chose HSIM for our sub-40-nanometer flow based on its advanced technologies for post-layout analysis and its ability to deliver accurate simulation results while maintaining fast throughput for our largest memory compilers."

"TSMC's selection of HSIM for their most advanced memory IP characterization validates our continued R&D investment in circuit simulation technologies," said Paul Lo, senior vice president and general manager of the Analog/Mixed-Signal Group at Synopsys. "Through collaboration with companies like TSMC, we are able to deliver solutions for our customers' toughest circuit verification challenges."