Spice-a-circuit 1000 times faster by using behavioral modeling tool Arana from Orora

Orora Design Technologies with support of Defense Advanced Research Projects Agency (DARPA), Defense Threat Reduction Agency, and Air Force Research Laboratory has made available a analog and mixed signal IC functional verification tool called Arana behavioral modeling platform. Arana extracts intelligent behavioral models in Verilog-A/MS/D from a circuit netlist, offering 100 times to 1000 times speedup for complex mixed-signal functional verification.

Analog/mixed-signal functional verification is made faster, efficient and intelligent with this new Arana software tool. Mixed-signal VLSI designers can quickly generate models but with less un-noticeable design errors.

Arana is already employed by over twenty semiconductor companies to do functional verification of analog semiconductor circuits including phase-locked loops, data converters (ADC, DAC), SerDes, DC-DC converters, memory, and custom-digital circuits.

"As a leading design house for high-performance defense and space electronics, we started to use Orora's tools in 2003," said Dr. Warren Snapp, director of Boeing's Phantom Work, Solid State Electronics Development. "Arana is the only tool that allows us to verify our 90nm radiation-hardened XAUI SerDes design. For a SerDes transmitter driver, Arana speeds up SPICE by 1200 times. With Arana behavioral models, we discovered several design errors that would otherwise have gone to fabrication."

"Behavioral modeling has been regarded as a strategic yet most difficult-to-use technology for mixed-signal design," according to Dr. Prasad Subramaniam, vice president of Design Technology, eSilicon Corporation. "Many groups adopting behavioral modeling have invested in manually creating behavioral models. Unfortunately, quality-modeling engineers are hard to find. Furthermore, it is difficult to maintain consistency between models and circuits. This is especially an issue for complex mixed-signal designs where analog circuits utilize extensive digital control, and have frequent specification changes up to the last minute," added Dr. Subramaniam. "With Arana, a designer without expert knowledge of behavioral modeling languages can quickly generate models consistent with his or her circuit design."

"In contrast, Arana is based on formulating circuit equations in the same way as any SPICE simulator, and then applying the rigorous theory of model abstraction," noted Dr. Richard Shi, the Arana architect. An elected fellow of IEEE, Dr. Shi participated in the creation of IEEE analog and mixed-signal (AMS) language industry standards, and has been recognized with the prestigious IEEE Donald O. Pederson Best Paper Award for his research on model order reduction.

"Verification often amounts to over half of the total chip design cost," added Dr. Shi. "Since most failures causing mixed-signal chip re-spins are due to simple connectivity and logic errors at the analog and digital interface, Arana provides an enabler for simulation-based mixed-signal function verification."

Arana is priced at $88,000 for a one-year time-based license. It's quite an expensive piece of EDA tool for the benefit of 1000 times circuit-simulation.