Teradici selects Synopsys' Galaxy and Discovery chip design tools

Teradici has selected Synopsys' Galaxy Implementation and Discovery Verification Platforms for their implementation, verification and analog/mixed-signal flows, and extended their use of Synopsys DesignWare IP cores and consulting services. Teradici Corporation makes innovative PC-over-IP display protocol technology that eliminates the need for desktop workstations, PCs and thin clients. The TERA Host and Portal processors (TERA1100 PC-over-IP Portal Processor and TERA1200 PC-over-IP Host Processor) uses advanced display compression algorithms and I/O bridging.

"Over the past several years, we have built a successful relationship with Synopsys by utilizing their best-in-class design tools, interface IP and design services to mitigate our project risks and accelerate the delivery of our breakthrough technology to our customers," said Maher Fahmi, vice president of Silicon Engineering and co-founder, Teradici Corporation. "As we grow our competencies in new areas such as analog design and simulation, we know we can continue to rely on the breadth and quality of Synopsys' technology and the outstanding support of its field and services teams."

In the past 4 months Synopsys has announced it's chip design software is selected by the semiconductor companies such as Achronix, NetLogic Microsystems, Aquantia, TriQuint Semiconductor, Exar, MediaTek, Toshiba, NVIDIA, Wolfson Microelectronics, Marvell, Priva Technologies. Some of these companies call Synopsys as primary EDA partner.

Synopsys has introduced the latest release of its Galaxy Implementation Platform delivering 2x faster design implementation and signoff throughput with new multicore performance and multi-corner/multi-mode (MCMM) technologies.