Mentor makes it's range of EDA tools to support new TSMC processes

To make the VLSI design software more open, semiconductor fab expert TSMC has released iPDK (interoperable process design kit) with open access database and data model. The iPDK supports open standard languages for scripting and programming by including complete views of symbols, parameterized layout cells, call backs, and technology files.

Mentor Graphics has announced support for the TSMC iPDK in the Mentor's Custom IC design flow products.

"The TSMC unified iPDK is designed to eliminate the need for multiple proprietary PDKs, and opens the door to greater innovations in custom, analog, mixed-signal and RF design," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC. "Support from the EDA community has been outstanding, and we feel the collaborative nature of the work will pay huge dividends to our mutual customers."

"The iPDK initiative is a great example of the industry working together in the best interest of its customers," said Robert Hum, general manager of Mentor Graphics Deep Submicron Division. "Design kits written in proprietary languages that keep the customer captive to one vendor do not serve the industry well. Interoperability gives a customer the choice and flexibility to buy the EDA tools that best serve their business objectives."

Mentor Graphics has also expanded the set of Mentor tools and technologies included in TSMC Reference Flow 10.0. supporting netlist-to-GDSII implementation for 28nm ICs introduced for testing.

"Mentor Graphics continues to expand its Reference Flow offerings to cover the total IC design cycle from the systems level through functional verification, place-and-route, physical verification and silicon test, as well as offering new solutions such as low power, manufacturing variability, and silicon yield analysis," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.

The Reference Flow 10.0 includes Mentor's Olympus-SoC place-and-route system and Calibre physical verification tool.

"The complete Mentor design-to-silicon track in TSMC's Reference Flow 10.0 allows us to address our mutual customers' biggest challenges for 28nm, including low power design and verification, large-scale SoC implementation, manufacturing variability, and cost-effective test and yield analysis," said Walden C. Rhines, chairman and CEO, Mentor Graphics. "The industry transition to 28nm processes also presents new technical challenges, which Mentor is in a unique position to solve. Our close collaboration with TSMC allows us to close the loop between designers and foundries with tools that help our customers get their products to market faster with higher performance and greater reliability."

Adding to the above two, Mentor Graphic's Calibre nmDRC and nmLVS offerings now support the interoperable iDRC and iLVS formats introduced by TSMC.

"The TSMC iDRC ands iLVS formats benefit both TSMC and its customers by making it possible to define and customize complex verification rules for each of our processes that can in turn drive verification tools from any supporting vendor," said ST Juang, senior director of Design Infrastructure Marketing at TSMC. "This enables us and our customers to easily adapt design rules to new requirements or special situations without worrying about tuning and testing for different tool flows. We've worked closely with Mentor on the architecture and syntax of iDRC and iLVS and have completed first validation on the Calibre tool suite as our lead physical verification platform."

"Our collaboration with TSMC on the definition of iDRC and iLVS helps our mutual customers realize the best possible performance from Calibre products," said Joseph Sawicki, vice president and general manager for the Design-to-Silicon division at Mentor Graphics. "With this collaboration, TSMC ensures their design guidelines are delivered in a consistent manner to all qualified vendors, and Mentor can use its proprietary technology to continue delivering industry-leading verification platforms with the fastest and most efficient underlying code possible."

Other leading chip design software vendor Synopsys had also made an announcement supporting several of the TSMC's new interoperable processes.