Synopsys VLSI chip design tool called IC validator which is part of its Galaxy platform now supports TSMC's new physical design verification format called iDRC (interoperable design rule checking) iLVS (interoperable layout versus schematic). Interoperability enables EDA tools to exchange chip-design content across different EDA platforms/environments. It's a like giving copy and paste kind of feature to VLSI designer to move the IP or such design content from one platform to other.
The highlighted features of IC validator tool are,
1. It supports efficient multicore-based computer on which it is installed.
2. It has a near-linear scalar hybrid sign off engine supporting complex polygon and edge based rules for node at 45nm 32nm & 28nm.
"Working with advanced node customers, TSMC and Synopsys concluded that a unified specification for Physical Verification tools was key to accelerating time to market, a primary benefit of TSMC's Open Innovation Platform," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC. "We benefited from the close cooperation with Synopsys, using IC Validator as the development and validation platform and a catalyst for the timely introduction of these formats."
"By eliminating qualification and consistency barriers and assuring timely access to technology files, this close collaboration between TSMC and Synopsys, with participation from other EDA vendors, clears the way for designers to easily select amongst available physical verification tools," said Bijan Kiani, vice president of product marketing, design and manufacturing products at Synopsys. "This puts Synopsys in a strong position to efficiently bring In-Design physical verification to our common customers."
The other physical verification tools in the market are Mentor's calibre cadence Assura/Dracula/Diva, and magma's Mojave Quartz. Calibre and IC validator is more popular among the folks compared to other two.
For more details visit www.synopsys.com.