Renesas' new SiP design software to verify signal integrity and heat dissipation

Renesas Technology has developed new design software tool for System in Package (SiP) developers, through which key characteristics, such as design quality, noise analysis and heat dispersion of semiconductor devices and other components inside the SiP can be analyzed.

This SiP Top-Down Design Environment integrates design-content and software tools, including a database of information on chips that can be incorporated in SiP products and a substrate layout tool. It provides a common user interface that enables transfer of data between design tools, and automates tasks such as analysis during circuit simulations. This SiP EDA tool reduces the design time of SiP module significantly.

Key product features:

1. Integrated design database and common user interface for multiple tools
The new design environment uses an integrated design database to provide unified management of design data and easy connections for analysis of electrical or heat dissipation characteristics. Thus, data on chip shapes and positions as well as chip-to-chip connection data can be extracted from the database and connected to the substrate layout tool. In turn, wire bonding and substrate pattern data from the substrate layout tool can be connected to other analysis tools. For enhanced ease of use, a common interface is provided for running the tools and making settings.

2. Noise analysis of large-scale package substrates at the initial design stage
This design software includes an electromagnetic field analysis tool that supports large-scale substrates. This means it is not necessary to divide up the area to be analyzed. In addition, simulation condition setting and result determination for circuit simulations are automated. It is therefore possible to estimate noise at the initial design stage based on the electrical characteristics.

3. Heat dispersion analysis taking substrate layout into account
This EDA tool extracts from the substrate layout data information on the conductor pattern area share (copper ratio), layer thickness, and materials of the internal SiP package wiring, power plane, etc., the number of via holes between layers, and the shapes and positions of the chips, and it automatically builds an environment for the heat dispersion evaluation package model. Another newly developed function applies the power consumption distribution of the SoC to the thermal analysis model so that the distribution of heat generation within the chips is taken into account. These advances not only increase the accuracy of the models, they make it possible to complete the thermal analysis in a short amount of time.

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