NEC develops new ADC architecture for better signal accuracy and smaller-size

NEC has developed a new technology to reduce the size of Analog to Digital Converters (ADCs) analog functional blocks in SoCs. These ADCs work in parallel to average and linearize the transfer characteristics. This new architecture is called folding ADCs

This new innovation by NEC Realizes digital error correction architecture through smooth digital transition of the two folding ADCs resulting in improved performance and low power consumption.

Additionally, the new ADC architecture adopts a digital calibration algorithm to correct the mismatches caused by the drift of environment and process variation, such as temperature changes. The new technology operates parallel with normal operation eliminating the need for additional calibration cycle.

Applying the new architecture to analog-to-digital converters (ADCs), NEC Electronics has developed a 6-bit, 2.7 Giga samples per second (Gsps) ADC using 90 nm process.

With this development, NEC can pack more and better-performing ADC interfaces in its future SoCs and microcontrollers.