Synposys tests its DDR3 IP on real silicon at data speeds of 1600 Mbps

Synopsys has verified its DesignWare DDR3/2 PHY and digital controller IP in test silicon at the JEDEC specified max rate of 1600 Megabits per second (Mbps). Synopsys has tested on DDR3 memory chips and DIMMs manufactured in 65-nanometer (nm) technology. Synopsys has used Elpida made 16-bit-wide DDR3-1600 SDRAMs

"We are pleased to help facilitate the successful verification of 1600 Mbps memory performance in Synopsys' DesignWare DDR3/2 characterization environment," said Susumu Hatano, executive manager for the System Technology Group at Elpida Memory, Inc. "DDR3 SDRAMs are just beginning to make headway into the embedded DRAM market, offering up to 50 percent higher bandwidth and over 15 to 30 percent lower power versus DDR2. Synopsys' silicon-proven DesignWare DDR3/2 IP will enable designers to take advantage of these benefits in their high-performance SoC designs."

"With DDR interfaces undergoing a doubling of speed approximately every three years, SoC designers are looking for proven IP solutions from a trusted supplier to help them meet their aggressive time-to-market goals," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "By offering a broad portfolio of high-quality, silicon-proven DDR IP supporting the full spectrum of speeds up to 1600 Mbps, Synopsys helps lower the risk of incorporating the latest memory interface into their designs."