Synopsys parallelizes and unifies
simulation and verification tasks of VLSI design
EDA industry is reeling under pressure to innovate. Semiconductor
vendors are in no-mood to pay hefty charges for some small
improvements. EDA vendors are left with limited options
either to provide cost optimized solution or powerful high
performance chip design software of 2x performance for same
cost. However, 10x performance improvement may allow the
vendor to rise the billing proportionally.
Either its a notebook, or netbook, or call it smart phone,
these convergence devices singularly got to provide functions
of communications (mainly wireless), computing and entertainment.
In VLSI and semiconductor language this is like analog,
RF and digital in one IC or simply call it System on Chip.
There is no dearth of opportunity in inventing such gadgets.
The challenge is Moore's law pressure. Many consumer type
customers buying electronics gadgets have unknowingly understood
the Moore's law concept. They may not know this law by its
name, but they know that technology grows at some rate and
the price fall at some rate every year.
Customer expects a smart phone costing X dollars this year
will be available by at least by 2/3X dollars a year later
or expects a performance boost of 1.5 to two times at the
same price. So the real pressure is cost.
When customer expectations are so high, the semiconductor
supplier also expects same from their EDA tool vendor. EDA
vendor Synopsys looks to be ahead of its competitors in
understanding this kind of market requirements.
Synopsys has released its updated version of simulation
and verification tools and has unified them into single
environment to give 4x performance boost compared to its
The new unified circuit simulation solution is called CustomSim.
CustomSim unifies NanoSim, HSIM, and XA into a single circuit
simulation solution. This tool is tuned to work on multicore-based
computer systems. Synopsys claims, CustomSim offer four
times (4x) performance improvement for large analog and
Unified simulation solutions such as this, speeds up and
simplify the design of today's complex System on Chip (SoC)
devices. By using CustomSim, VLSI design engineers can verify
different types of circuits, including custom digital, analog
and memory with some special analog functions such as RF
transceivers, PLLs and Sigma Delta Converters. The CustomSim
employs Direct Kernel Integration to Synopsys' VCS simulator
for full-chip verification. The solution is integrated into
a unified AMS verification environment simplifying usability
through a common set of inputs, outputs, device models and
On the verification front, Synopsys released latest verification
platform called Discovery 2009. Discovery 2009 features
support for new multicore simulation technologies, native
design checks and low power verification. VCS functional
verification and CustomSim unified circuit simulation solutions
both are key components of the Discovery platform. Synopsys
claims Discovery 2009 deliver up to four times faster verification
than previous solutions.
Discovery 2009 incorporates comprehensive low-power verification
capabilities at multiple levels of abstraction, from RTL
to transistor level. VCS with MVSIM delivers true voltage-aware
RTL and gate-level simulation, automated assertions, and
comprehensive verification coverage as defined in the new
Verification Methodology Manual for Low Power (VMM-LP) book.
Synopsys ups the speed of both major chip design tasks
of simulation and verification by parallelizing the tasks
on multicore systems.
Synopsys says, "VCS multicore technology delivers
a two-times (2x) improvement in verification performance
by harnessing the power of multicore CPUs. The new technology
removes performance bottlenecks and speeds verification
by distributing time-consuming activities across multiple
cores. VCS multicore technology combines the speed-up from
parallel computation with the industry-leading Native Testbench
(NTB) compiler to meet the performance requirements for
the verification of large-scale designs. This enhancement
helps verification teams address the growing challenges
of verifying increasingly complex designs and achieving
first-pass silicon success."
When this writer asked Manoj Gandhi , Senior VP and GM
of verification group, How Synopsys register better revenue
figures than its competitors during this odd times? He said,
Synopsys follows a different sales model, which is conservative
compared others in the industry.
Synopsys has the advantage of having big and smart Indian
teams working in Bangalore and Hyderabad. These two cities
and Noida in U.P have become major places to hunt for Indian
VLSI design engineers and software programmers. The advantage
of low cost but highly skilled VLSI talent available in
India is well utilized by Synopsys. The big chunk of their
development is carried from these two centers.
VLSI-design-related EDA software design is not ordinary,
the companies and engineers are a rank higher than anybody
else in electronics industry. They are simply extra-ordinary.
It's pure tech industry. But however talent they are, the
market only determines their revenue prospects. Connecting
their talent to the market requirement is the challenge
for them at this odd economic condition. So innovation in
this industry has to address both technology and market.