12th Feb 09
Synopsys timing analysis tool to
support multicore
Synopsys unveiled two key improvements to its PrimeTime
static timing analysis (STA) suite to improve performance.
The latest release supports multicore processing technology
that makes more effective use of both single-core and multicore
CPUs across today's compute server farms, harnessing their
computing potential. This release also introduces new runtime
optimizations, allowing design engineers to run faster full
timing and signal integrity (SI) analysis on their large
designs early in the implementation process, thus reducing
costly design closure iterations. These improvements work
in concert to deliver up to 2X faster runtime and have been
confirmed on a suite of leading semiconductor companies'
designs ranging in size from one million to 50 million instances.
"We worked closely with Synopsys to achieve significant
runtime improvements with PrimeTime over the last several
releases," said Senthil Krishnasamy, director of Physical
Design, AMD. "We are encouraged by the initial results
of the new PrimeTime multicore feature, and look forward
to deploying it to accelerate the STA analysis of our large
designs by more fully utilizing the potential of Quad-Core
AMD Opteron processors in our silicon design process."
In today's design environment, the typical compute server
farm is comprised of a mix of legacy single-core and newer
multicore CPU machines. Access to these heterogeneous resources
is typically provided through job scheduling systems that
help ensure the most efficient allocation based on dynamically-changing,
enterprise-wide compute needs. During periods of high activity
in the farm, the wait time for available multicore machines
can far outweigh the runtime speed-up gained by multicore
acceleration. Synopsys' multicore capability in PrimeTime
2008.12 helps provide the flexibility to utilize any idle
CPU core resource, on any machine in the farm. This enables
multicore acceleration without the multicore machine access
time penalty, which means more timing analysis jobs completed
faster and more efficiently.
"At RMI, time-to-market is mission critical for our
platform of high-performance multi-core multi-threaded SoC
processors," said Ramon Macias, director of physical
design, RMI. "In order to achieve fast design closure
on our latest multi-million instance 40-nanometer design,
we need to run signal integrity analysis early in our design
implementation phase to minimize ECOs during signoff. The
latest runtime optimizations in PrimeTime SI combined with
multicore CPU support has improved our runtimes by 1.5 to
1.8X."
Design teams targeting the latest silicon process technology
nodes see a significant productivity benefit when they incorporate
SI analysis early in their design implementation phase.
Waiting until timing signoff to perform full-chip SI analysis
can result in too many violations, introducing a major design
closure bottleneck late in the design cycle. New runtime
optimizations in the latest PrimeTime release are targeted
specifically at making SI analysis of large designs more
practical in the earlier phases of design implementation,
accelerating signoff closure.
"The latest PrimeTime release demonstrates how Synopsys'
R&D continues to innovate and execute on our multicore
initiative," said Antun Domic, senior vice president
and general manager, Implementation Group at Synopsys. "Through
continuous R&D investment, we have addressed a key STA
and SI analysis challenge for our customers - utilizing
CPU cores across machines to accelerate runtime. Companies
can now make more effective use of their existing compute
server farms while having the flexibility to take advantage
of the latest multicore hardware."
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