ee Herald                                           
Home | News | New Products | India Specific | Design Guide | Sourcing database | Student Section | About us | Contact us | What's New
Processor / MCU / DSP
Memory
Analog
Logic and Interface
PLD / FPGA
Power-supply and Industrial ICs
Automotive ICs
Cellphone ICs
Consumer ICs
Computer ICs
Communication ICs (Data & Analog)
RF / Microwave
Subsystems / Boards
Reference Design
Software / Development kits
Test and Measurement
Discrete
Opto
Passives
Interconnect
Sensors
Batteries
Others

News

   12th Feb 09

 Einfochips and NoBug offer verification IP services for Synopsys customers

India based eInfochips, and East Europe's NoBug, both VLSI design services companies are first two members of a newly formed alliance called DesignWare Verification IP (VIP) Alliance by EDA company Synopsys. These two companies through this alliance program offer VLSI designers a range of Verification Methodology Manual (VMM)-enabled verification IP, complementing the Synopsys DesignWare verification IP portfolio.


The VIP offered by these members through the DesignWare VIP Alliance will be developed in accordance with the guidelines used by Synopsys' verification IP engineering experts. Also the members will use Synopsys' internal VIP VMM rating tool. The VMM features included in the Alliance members' VIP provide easy integration into SystemVerilog VMM verification environments, helping to speed testbench development time.

"We have been developing verification IP for many years and have seen wide adoption of VMM as well as an increasing demand for VMM-enabled verification IP," said Sribash Dey, vice president of Sales at eInfochips. "By working closely with Synopsys, our mutual customers can have access to a wider range of VMM-enabled Verification IP that helps accelerate their verification process."

"With such high activity around VMM, it's important to provide designers with verification IP to meet their design requirements," said Moshe Shalev, NoBug's CEO. "As a DesignWare VIP Alliance member with access to the guidelines and VMM rating tool used by Synopsys, we will be able to provide VIP that is complementary to DesignWare VIP and meets the high-quality expectations of our mutual clients."

"The DesignWare VIP Alliance members have gained our confidence through their experience in VMM-enabled verification IP development, and we trust their ability to provide our mutual customers with essential verification IP and services," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "This Alliance enables designers to have easy access to pre-qualified vendors for their Verification IP needs and helps them accelerate the adoption of new technologies into their SoCs with less risk."

 



Events
Advertise
Send News
Send Article
Feedback
eeherald.com
India Search
electronic components
Home | News | New Products | India Specific | Design Guide | Sourcing database | Student Section | About us | Contact us | What's New
©2006 Electronics Engineering Herald