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News

   11th Feb 09

 Toshiba achieves 3-bit-per-cell 32Gb record in NAND Flash capacity

Using 32 nanometer (nm) generation, Toshiba has realized a 3-bit-per-cell 32 gigabit (Gb)1 chip with the world-smallest die size, and smaller than a 2-bit-per-cell 16Gb chip fabricated with 43nm technology, which is currently in the market. This new chip will be mass-produced in the second half of 2009. The company has also fabricated the world's first 64Gb chip that applies 4-bit-per-cell technology at the 43 nm process generations.

The 3-bit-per-cell 32nm generation device uses optimized circuit design for the row decoder and extended column architecture, which significantly contributed to a 113mm2 chip, the smallest die size yet achieved in this generation. The 4-bit-per cell applies super multi-bit programming technologies, which realizes 64Gb without increase in chip size, while achieving a write speed performance of 7.8MB/s.




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