Technology to transfer data from DRAM chips to processor @ 1 terabyte per second

The semiconductor memory IP expert Rambus has pioneered a new memory signaling technologies useful for the development of a future memory architecture capable of delivering a terabyte per second of memory bandwidth (1 terabyte = 1,024 gigabytes) to a single System-on-Chip (SoC).

To achieve 1 TByte/s memory bandwidth, Rambus has developed fundamental innovations that include,

1.  32X Data Rate - A new memory signaling technology which transmits 32 data bits per input clock          cycle.
2.  Fully Differential Memory Architecture (FDMA) - Providing the benefits of differential signaling on both      the DQ (data) and C/A (command/address) channels
3.  FlexLink C/A - The industry's first full speed, scalable, point-to-point command/address link.

Faster, multi-core processor-based systems require greatly increased memory performance over systems built around single-core processor. Without adequate bandwidth, memory systems will be the limiting factor in delivering the required performance desired in next-generation consumer and computing systems. As an example, graphics processors currently require as much as 128GBytes/s of memory bandwidth and are targeting 500 GBytes/s in the near future. The current generation of gaming system uses 25-50 GBytes/s of memory bandwidth. Over the next 4-5 years, graphics and gaming console will push memory bandwidth needs towards 1 TByte/s.

Rambus' innovative 32X data rate technology transmits 32 bits of data per clock cycle on each I/O. Conventional double data rate memory systems transfer two bits of data, per I/O, every clock cycle. While double data rate memory architectures can achieve a one gigabit per second transfer rate with a 500 MHz clock, 32X Data Rate enables an amazing 16Gbps signaling rate using the same 500 MHz clock.