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Date: Dec 13, 06
IBM and AMD expect first 45nm chips to be available in mid-2008.
At International Electronic Device Meeting, IBM and AMD have presented papers on immersion lithography, use of ultra-low- K dielectric, and multiple enhanced transistor strain techniques at 45nm nodes.
In immersion lithography, the medium through which the light or any such wave passing between the lens and silicon wafer is not vacuum or air but it’s a transparent liquid (can be pure H2O too) with a refractive index suitable for 45nm lithography.
The low K dielectric will reduce the signal interference and other such very high frequency disturbances across the connecting leads on the wafer.
The one more feature called strained silicon will raise current capacities of switching transistors.
These three techniques are simple magic to reach higher integration and speed with not much alteration in lithography equipment.
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