Chip design EDA: The three popular and latest P&R tools for advanced nodes
Date: 15/12/2023
Synopsys IC Compiler II also referred as ICC2, Cadence Innovus, and Siemens-EDA Aprisa are the three only leading commercial Place and Route (P&R) tools for physical design dominating the deep node digital VLSI chip market:
Synopsys IC Compiler II is one of the widely used P&R tool across the semiconductor chip industry by IDMs and fables SoC makers:
IC Compiler II is a game-changing successor to Synopsys IC Compiler covering both mature and deep nodes which is built from scratch with new algorithms.
IC Compiler II features very high-capacity design planning, unique clock-building technology and advanced global-analytical closure techniques.
It can handle 100s of millions of instances by using multi-threaded infrastructure.
IC Compiler II features block-level functionality powered by global-analytical optimization engine, a totally new clock generator and unique algorithmic capabilities in post-route optimization delivering enhanced quality of results (QoR) in PPA.
Other features include: low memory footprint, context-aware clock tree synthesis, advanced electro-migration (EM) optimization, native support for mesh and multi-source topologies.
Cadence Innovus:
This tool is also developed from scratch. It uses a placement engine called Cadence-GigaPlace, a solver-based placement technology, and a optimization engine called Cadence-GigaOpt, a multi-threaded, layer-aware optimization engine. It uses a unique mixed-macro and standard-cell placement capability.
Innovus uses massive parallel architecture with multi-threading.
Innovus employ NanoRoute engine to achieve signal integrity early on and improves post-route correlation.
Other features:
Concurrent electrical and physical optimization.
Offers mixed-macro and standard-cell placement
Cadence-Genus Synthesis Solution is tightly integrated with the Innovus system and also Cadence-Tempus Timing Signoff Solution, Cadence-Quantus Extraction Solution, and Cadence-Voltus IC Power Integrity Solution are integrated with the Innovus system.
Takes care of IR and EM violations by having power integrity-aware placement, optimization, clock tree, and routing features.
Though not as popular as these above two, the new Aprisa from Siemens EDA is pitted as another alternative in P and R.
Aprisa uses detail-route-centric architecture and hierarchical database for faster design closure and optimal QoR with lesser iterations. Aprisa support low power design semiconductor IC as a primary design. Siemens stated in its page "Whether your goal is to speed time to tapeout, reduce total cost of ownership, or achieve the lowest power usage, Aprisa is here with patented technology and best-in-class support to ensure your success."
