Silicon IP cores optimized for metaverse and other AR/VR glasses
Date: 25/10/2022
If you are cutting edge semiconductor design engineer and developing chips for an extreme low power consuming wearable Metaverse Extended Reality (XR) integrated personal devices. Then you can speed up such development by using readily available Silicon IP cores from Belgium based easics NV.
easics is offering IP solution named nearAI for battery-powered extended reality devices. These PPA optimized digital semiconductor IP cores deliver low-power, low latency, and low Silicon area, what easics calls as L3 optimiser technology. These digital IP cores are optimised to readily integrate into wide range of complex semiconductor ICs such as ASICs, ASSPs and system on chips.
These IPs enable development of XR devices with a response time matching human senses, where they digitally process the signals such as video from the camera and audio from microphones with very low latency using DSPs and image sensor silicon. easics says it is like instant visual and aural feedback to the user.
Most of the market researchers forecast, by year 2026 tens of millions of metaverse like augmented reality and virtual reality integrated wearable personal devices to be sold in the global market. These devices to integrate a lot of edge AI to process data from sensors and add intelligency at every level.
In this extremely complex technology and mostly un-navigated areas of product development, optimising and proven silicon IP comes handy to develop products in short time. The well known chip design parameter PPA (power-performance-area) is optimized to its best.
Easics calls this family as "nearbAI" IP cores, having lot of artificial intelligency related capabilities and features such as neural network inference engines, configurable for a wide range of AI models and use cases optimized for energy consumption, performance and area. These IPs support smart human brain like processing functions such as scene segmentation and reconstruction, object and face detection and recognition by using itS L3 technology.
The latency is so good face detection is possible within 2 ms. And they offer a record-breaking DSP MAC utilization up to 95% with wide-ranging configurable number of MACs in the range of 16 to 4096. MAC accuracy can be configurable with independent coefficient and data quantisation, supporting 4 to 16 bit and single bit granularity. Internal memory bank sizes can be configurable and also Bus widths can be configurable. When it comes to power consumption it can be as low as sub 10 milliwatt.
These IPs also support continuous multiplexing between multiple neural networks on the same nearbAI core saving silicon area.
Sensors such such as RGB, ToF, NIR, thermal IR, LiDAR, hyperspectral, stereo, ultrasound, audio are supported.
Can read your neural network in ONNX format using TensorFlow, Keras, PyTorch and mxnet.
Some more advantages include: Fast FPGA prototyping, no need of additional XR accelerator chips, supports offload engine processor outside IP core, secure OTA update and cloud interoperability.
“nearbAI is unique, delivering best-in-class extreme edge AI inference solutions for XR devices. It builds on more than three decades of DSP and image sensor chip design. Our mission is to provide customers with Ips that perfectly fit their specifications, offer outstanding performance, and are seamless to integrate right through to tape-out easics is committed to bringing the most advanced technology and solutions to market. With nearbAI, along with our partners and customers, we are pushing the latest AI innovation to the extreme edge”, said Ramses Valvekens, CSO & Managing Director at easics.
