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Date: 24-11-20

Open FPGA stack from Intel for hardware accelerators

FPGA Business unit of Intel has announced a new open FPGA stack providing infrastructure-code for programmable silicon and software  to develop FPGA-based hardware accelerators for computing platforms.  This code is developed using open source development  methodology and delivered through git repositories.

Ease of development and scalability are the key features of this offer.  Intel says developers only need to implement  blocks relevant to the design. Developers can also build application-specific FPGA designs using this composable hardware code. These "shells" cover key memory networking CPU and data-path. OFS employs AXI interfaces so that IP can be reusable.  Software scalability is achieved by having support for both bare metal and virtualised deployment models.    

Dave Moore, Intel corporate vice president and general manager of the Programmable Solutions Group says “FPGAs have always and continue to enable developers to deliver customized hardware with optimal power, performance and TCO for workloads from the edge to the cloud. With the proven success from our early-access customers, we are excited to launch the Intel Open FPGA Stack, with its demonstrated ability to dramatically both reduce the development time and also increase code and hardware design reuse for customers and partners looking to accelerate their workloads.”

Open source Linux distribution vendors can provide native support to third-party and proprietary Intel-OFS platforms, due to Intel OFS providing open-sourced and upstreamed code to the Linux kernel.

This OFS infrastructure with standard interfaces can be shared commonly between circuit board developers, ODMs and customers in the process of development.  The OFS platform saves resources and effort for application developers to port their developed application across different Intel OFS-based platforms. The open-source software vendors also can leverage Intel’s open-sourced and upstreamed code to expand support for FPGAs as they do for CPUs and GPUs under existing and new contracts.

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