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Date: 22-09-17

Open-Silicon completed silicon validation of its HBM2 IP subsystem in TSMC's 16nm

Open-Silicon said it has completed silicon validation of its High Bandwidth Memory (HBM2) IP subsystem in TSMC's 16nm FinFET technology in combination with TSMC's CoWoS 2.5D silicon interposer technology and HBM2 memory.

Details shared by Open-Silicon in its release:

This full IP subsystem solution includes an HBM2 controller, PHY and interposer I/O, and completes the critical components needed for the successful integration of HBM2 memory into ASIC system-in-package (SiP) designs. Silicon results of the 2.5D HBM2 ASIC SiP validation/evaluation platform will be presented via a technical paper titled, "High Bandwidth Memory (HBM2) IP Subsystem Silicon Validation and Interoperability with HBM2 Memory Die Stack" at the TSMC Open Innovation Platform® (OIP) Ecosystem Forum on September 13, 2017, in Santa Clara, CA. The solution will also be demonstrated at Open-Silicon's booth at the event.

This silicon validation demonstrates functional validation and interoperability between Open-Silicon's HBM2 IP subsystem and HBM2 memory. Data rates of 1.6Gbps/2Gbps were successfully achieved on the HBM2 SiP solution in TSMC's 16nm technology.

The HBM2 IP subsystem solution is available for 2.5D ASIC design starts and also as a licensable Intellectual Property (IP) subsystem.

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