LA1575, the first chip from the family of the new Layerscape from NXP Semiconductors solves a multi-standard problem with simultaneous implementation of 802.11ax, 802.11ad, and millimeter wave (mmWave) standards on a single SoC device. This IC chip is initially targeted at enterprise and high-end home gateway markets. LA1575 packs fully programmable PHY and MAC with acceleration technologies for 5G, Wi-Fi and wireline protocols that allow updates, changes, and new features to be added via simple software upgrades.
The engineers can use the pre-ratified version of standards and can update their end products quickly via software to final release versions with differentiated features.
“A fully programmable PHY and MAC is game-changing technology that will fundamentally impact the way new standards are implemented,” said Tareq Bustami, senior vice president and general manager at NXP Semiconductors. “Ultimately, we will enable solution providers to deploy fully programmable systems capable of connecting clients at the speeds they expect over virtually any access technology. Early customer engagements on the LA1575 validate the benefits of our overall solution.”
“Extending NXP’s 64-bit ARM portfolio by including physical- and MAC-layer processing, the LA1575 builds upon the company’s deep experience in processing, wireless technologies, and networking infrastructure,” said Jag Bolaria, principal analyst for embedded at The Linley Group. “This new offering reinforces NXP’s position as a leading supplier of one of the broadest portfolios of ARM 64-bit networking solutions.”
By having programmable acceleration feature with dynamic PHY and MAC resource allocation across protocols in systems complying with power over Ethernet solution requirements, the LA1575 also has these other key advantages:
Performance matching hard-wired solutions, software-based features flexibility and leverages extensive third party ecosystem providers and the rich library base for Layerscape and ARM 64-bit cores.
LA1575 uses latest acceleration and secure platform technologies, packet offload and physical layer processing.
NXP to sample these chips in the month of April 2017