Systems-on-chip (SOC) vendor Octasic has licensed Arteris FlexNoC interconnect IP from Arteris for designing semiconductor SoC chips in tactical and industrial applications. The SOC design where the number of cores and peripherals are higher in number and also facing bandwidths and on –chip interconnect challenge, Arteris FlexNoc interconnect IP is relevant to design soc chip with less effort. The benefit of this FlexNoC interconnect IP according to Octasic is to reduce wire routing congestion while guaranteeing the bandwidth and latency of critical traffic. Arteris FlexNoC interconnect IP chosen by Octasic development team allowed them to increase scalability of their SoC architecture easily while avoiding bottleneck performance and wire routing congestion issues. Doug Morrissey, vice president and chief technology officer at Octasic says, “The number of cores and peripherals in our new SoC products and their associated requirements for massive and predictable data bandwidth made the on-chip interconnect a key design challenge in our project”. “The Arteris FlexNoC interconnect IP has proven that it can reduce wire routing congestion while guaranteeing the bandwidth and latency of critical traffic in our design with minimal effort on our part”.