The major cause of road accidents is human error, that's the main reason for the growth of advanced driver assistance systems(ADAS) and self driving vehicle technology. Whether it is driver assistance systems or self driving vehicle, it's the VLSI semiconductor chips, sensors and the loaded embedded software which takes over the tasks from human driver. In VLSI chip design process flow there is lesser chance of human error because of level of design automation software employment, and its automation, automation and automation and ever continuing automation… to design the chip and also to test the chip to make compliant with standards such as ISO 26262. At this year's 17th annual Synopsys User’s Group (SNUG) conference held in India the focus is further and further on automation, so that you can design very complex but yet robust and reliable semiconductor VLSI chips to automate car/vehicle driving. If you look at the semiconductor market, most of the market analysts have forecasted same or lesser global semiconductor revenue growth in year 2016 compared to 2015. This is due to negative growth in PC market and very little growth in wireless/smart phone market. It's the automotive electronics market which has potential to provide double-digit growth to semiconductor companies. That's the reason why the leading EDA vendor Synopsys is focusing heavily on automotive chip design automation and testing. Deirdre Hanford, Executive Vice President, Customer Engagement, Synopsys told this writer, Synopsys seeing significant increase in VLSI design activity in the automotive space. Her company focusing on automotive applications by providing software and IP targeting automotive electronics market. What matters in the automotive and such high-reliability applications is not only robust design but also thorough testing. Chip companies are now hurrying up to bring the chip faster to the market, but all the tests need to done before the chip getting into action. Synopsys has come out with new enhanced version of its ATPG (Automatic test pattern generation) and diagnostics software TetraMAX II to generate test patterns very faster cutting ATPG runtime from days to hours. TetraMAX II also generates 25 percent fewer patterns helping in saving the time and cost of testing IC chips. TetraMAX II utilizes all server cores regardless of design size. The tool also supports reuse of production proven design modeling and rule checking infrastructure, as well as user and tool interfaces, ensures designers can quickly deploy TetraMAX II risk-free on their most challenging designs.