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New Products

  Date: 19/06/2016

VLSI design: New version PowerDRC/LVS 2.2.1 released by POLYTEDA

POLYTEDA LLC released the latest version of its VLSI design software PowerDRC/LVS version 2.2.1 for design rule checking (DRC), layout vs. schematic checking (LVS) of VLSI chips. The PowerDRC/LVS version 2.2.1 supports hierarchical processing of cell arrays and standard cells multi-CPU mode.

The other features added to this new version includes:

1. Added support of number and string variables in PWRL along with conditional directives #if / #else

2. Added preprocessor directives #define, #ifdef, #ifndef for conditional rule compilation

3. Added $overunder and $underover options to $size

4. Added an example of using parameters extraction for the assessment of parasitic capacitances
5. Added support of extraction devices by nets

5. Added a lot of minor improvements for integration with Cadence Virtuoso

PowerDRC/LVS support semiconductor fabrication notes up to 40nm. PowerDRC/LVS he said to achieve higher scalability and turnaround time through the use of a unique data structure and native window scanning technique.

The release version is officially available from POLYTEDA.
For more information visit:

www.polyteda.com.




 
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