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Date: 12-06-16

QuickLogic' EOS S3 sensor processing SoC in production

QuickLogic announced successful completion of production qualification testing for its new EOS S3 sensor processing SoC, where initial shipments to support pre-production requirements to its tier1 customer scheduled for later this month. The multi-core SoC EOS S3 handles concurrent sensor applications, from basic to high computation algorithms for smartphone, wearable, and Internet of Things (IoT) devices. Compared to microcontroller, the EOS S3 sensor SoC features algorithm partitioning to consume the lowest possible power for a designated task. QuickLogic claims advanced sensor algorithms such as voice triggering, motion compensated heart rate monitoring, and indoor navigation can be implemented at significantly lower levels of power consumption compared to MCU chips. "The EOS S3 employs always-on, context-aware sensing capabilities while staying well within the strict power budgets of smartphone, wearable, and IoT designs," said Brian Faith, vice president of worldwide marketing at QuickLogic Corporation. "Now that this leading edge platform has been production qualified, the top-tier OEMs we've been working with know that they can reliably scale up their manufacturing to high-volume production levels." Key Features Feature Details Processor Cores - 578 KB of aggregate SRAM for code and data storage QuickLogic Proprietary microDSP Flexible Fusion Engine - 50 KB SRAM for code - 16 KB SRAM for data - Very Long Instruction Word (VLIW) microDSP architecture - 30 microWatts/MHz ARM Cortex M4F - Up to 80 MHz - Up to 512 KB SRAM - 32-Bit, includes Floating Point Unit - 75 microWatts/MHz Programmable Logic - 2,800 Effective logic cells Integrated Voice - Always-On Voice Trigger and Integrated Phrase Recognition Capability, based on Sensory TrulyHandsFree® technology - Integrated I2S and PDM microphone input with support for mono and stereo configurations - Integrated PDM to PCM conversion - Integrated Sensory Low Power Sound Detector (LPSD) - Optional PDM bypass mode to directly drive application processor or CODEC Interface Support To Host - Integrated SPI Slave To Sensors and Peripherals - Integrated SPI Master (2X), I2C, UART To Microphones - Integrated PDM and I2S Additional Components ADC - Integrated 12-Bit Sigma Delta Regulator - Integrated Low Drop Out (LDO), with 1.8 to 3.6 V input support System Clock - Integrated 32 kHz and High Speed Oscillator Package Configurations Ball Grid Array (BGA) - 3.5 x 3.5 mm x 0.7 mm, 0.40 mm ball pitch, - 64-ball, 46 user I/O's Wafer Level Chip Scale Package (WLCSP) - 2.7 x 2.4 mm x 0.6 mm, 0.35 mm ball pitch, - 42-ball, 27 user I/O's Development Environment - Industry Standard, IAR and Eclipse IDE Plugin Software Support - Supports Android Lollipop and Marshmallow operating systems QuickLogic's EOS S3 Sensor Processing SoC and design tools are available now. For additional information visit www.quicklogic.com/platforms/sensor-processing/eos/

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