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Date: 31-05-16

Thinner substrate material for semiconductor chip packaging

You can reduce the size of SOC chips not only by using smaller nodes, but also by using advanced semiconductor packaging materials. A new substrate material developed by Panasonic for use in semiconductor packaging makes the integrated circuit chips thinner and also cheaper. Panasonic is producing this material in volumes starting from June 2016.

chip material

MEGTRON GX series features reduced internal stress with no risk of causing warpage. Warpage when heated from 25 Deg C (room temperature) to 260 Deg C: max. 110 μm compared to 235 μm of Panasonic's convensional product.

This new substrate material is suggested for use in wide range of semiconductor packages such as PoP, MCP, SiP without bothering about IC chip size or substrate thickness. The reliability of connection between IC chips and package substrates is also better.

The market driving this technology is the trend of using thinner smart phones which demand thinner SoC chips. Panasonic has used a resin technology designed to minimize internal stress.

The substrate material eliminates the need for special warp-preventing glass cloth, thus contributing to a cut in the cost of the semiconductor package.

Panasonic is displaying this semiconductor material innovation at ECTC 2016, held at the Cosmopolitan of Las Vegas in the US from May 31 to June 3, 2016, and at the JPCA Show 2016, held at Tokyo
Big Sight, from June 1 to June 3.
To learn more about this visit the Panasonic website
http://www.panasonic.com/global

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