JEDEC Solid State Technology Association published newly revised standard that establishes requirements for the next generation of semiconductor device package components: JESD30G. Developed by JEDEC’s JC-11 Committee for Mechanical Standardization, the standard is based on a language used to describe the geometric aspect of the components used for semiconductor package development. JESD30G is available for free download from the JEDEC website.
The semiconductor device package language defines the component around the three pillars of package, lead form and lead position, providing a clear description of the component geometry. This standard provides the opportunity to encourage the industry to unify towards a single defining structure for components by adhering to a comprehensive, robust definition based on geometric data. This approach defines a majority of the components in the market, including scalability to support emerging and future semiconductor packages. This methodology defines the components in detail to enable process efficiencies throughout the product development process – from design, purchasing, manufacturing, test, and the entire product lifecycle. Additional definitions and clarifications of the device to support the industry will also be available in this requirements release.
John Kelly, JEDEC President, said, “These clearly defined requirements will eliminate duplicate or varying component definitions by using a geometric description to establish this industry standard. As a result, manufacturers will be able to develop products with greater confidence and optimal performance based on this standard.”
JEDEC standards and publications serve public interest by educating manufacturers and purchasing teams by improving product development and performance. This aids purchasers in the selection of products that adhere to quality standards for use in the microelectronics industry. JESD30G will facilitate better collaboration between component manufacturers and its customers throughout the product development process. Other standards bodies can also use this definition to drive recommendations on how components can be assembled into products, rules for land pattern shapes, assembly and inspection criteria, and to establish reliability standards for specific product development.
A.J. Incorvaia, vice president of Mentor Graphics Systems Design Division, stated, “As a JEDEC member, we see this new standard as a big step towards unifying the language used to describe parts throughout the component and product life cycle. This comprehensive language will scale with the constant emergence of new packages, benefiting the electronic industry by eliminating confusion and improving collaboration.”
A technology webinar on this new standard, co-presented by John Norton, Hewlett-Packard Enterprise Company (Chairman of JC-11) and Michael Durkan, Mentor Graphics (a key author of the new standard) will be held on February 23, 2016. To register for this event, go to: https://www.mentor.com/pcb/events/understanding-the-requirements-in-jesd30g-for-semiconductor-device-packages.
News Source: JEDEC