Wondering is there any source of low cost FPGA with some good performance. Well, you have now a couple of FPGA chips from China based FPGA startup Gowin Semiconductor offering mid range FPGAs called GW series manufactured by TSMC foundry. The most recent using TSMC 55nm embedded flash process.
GW1N family follows earlier version GW2A.GW1N has on chip user flash memory block which can be randomly accessed by user logic just as a normal NOR flash memory. The flash inside GW1N FPGA supports 10 years data retention and 10 thousands cycle's endurance for the cells.
GW1N-9K has up to 9K LUTs, up to 198K embedded block SRAM bits and nearly 20K Shadow SRAM bits; up to 2 Million user flash memory bits; up to 20 dedicated 18x18 multipliers and accumulators; up to 276 I/O which include 44 true LVDS output. It also support PLLs and DLLs applications.
Where as the GW2A-55K device contains about 55 thousand LUTs, 2.5 Million bits of Embedded Block Memory, 55 thousand bits Shadow Memory, 40 Dedicated 18x18 Multipliers, 498 single ended IO with additional 52 pair of dedicated LVDS IOs. It offers 2 packages: 1156PBGA and 484PBGA. Support wide range IO protocols such as DDR2, DDR3, ADC, Video, SPI4 etc.
GW1N available in WLCSP25, QFN32, LQFP100, LQFPQ44, MBGA160, BGA204, PBGA256, and PBGA484. The “instant on” featured GW1N supports 2 type of core Vcc devices - LV device and UV device. It supports many IO standards and protocols. It supports JTAG MSPI configuration. It supports dual boot option.
Targeted applications include consumer electronics, industry control, and automobile industry.
Jason Zhu, VP and CTO of Gowin Semiconductor Corp., says "Gowin's non-volatile offering is fully optimized on architecture, performance, and power. We believe GW1N family will help us greatly in penetrating these market segments mentioned above.”
The software supporting these FPGAs is Synplify from Synopsys. The backend of the design flow is supported by Gowin Semiconductor's own GOWIN tools covering HDL/RTL to bit stream data file generation, the entire design flow.