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Date: 05-08-15

20x faster time-based RTL power analysis by Cadence

VLSI chip designer can now analyze power consumption accurately during design exploration by using Cadence Joules RTL Power Solution. This new register-transfer level (RTL) power analysis software churn out the data 20X faster using time-based RTL power analysis tech compared to other methods, claims Cadence.

Joules RTL Power Solution handles up to 20 million instances overnight with gate-level accuracy within 15 percent of final power as signed off in the Cadence Voltus IC Power Integrity Solution. Joules RTL Power Solution integrates seamlessly with the Cadence Palladium emulation platform and the Stratus High-Level Synthesis (HLS) platform for early system-level power analysis and optimization.

Key highlights of the Joules RTL Power Solution as shared by Cadence:
Accurate RTL power estimation—The Joules RTL Power Solution performs an ultra-fast design synthesis using a new integrated prototype mode of the Genus Synthesis Solution, including physically aware clock tree and datapath buffering, and enabling accurate RTL power estimation.
Multi-threaded frame-based architecture—Power analysis is parallelized across multiple CPUs accelerating in-depth power exploration. Multiple stimulus files can be analyzed simultaneously and each stimulus file can be time-sliced into frames to enable time-based power reporting.
Adjustable power analysis resolution—User-selectable frames can be used to zoom in on power-critical periods of the simulation, and multiple stimuli for different design hierarchies can be merged to mimic full SoC traffic and power consumption. This enables design teams to easily analyze critical power problems.
Advanced data mining and debug—Power can be reported at the bit level or register level and may be categorized based on logic cell type, design hierarchy, clock domain, power domain or timing mode. A rich suite of library analysis and profiling tools is also included.
Early system-level power analysis—The Joules RTL Power Solution can be used within the Palladium Dynamic Power Analysis for more accurate time-based power calculations. This provides enhanced production-correlated peak and average power analysis, enabling design teams to analyze system power of software running on hardware early in the development cycle. The Joules RTL Power Solution is also integrated with the Stratus HLS platform for earlier and more accurate power estimates, enabling IP teams to better evaluate system-level micro-architectural tradeoffs.

“We see a significant opportunity to improve the capacity and accuracy of power analysis during system-level design exploration,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “The Joules RTL Power Solution combines the strength of our production implementation flow with parallel stimulation file processing to offer a power analysis solution that is fast enough for system-level analysis, yet correlates well to signoff results.”

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