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Date: 21-05-15

Direct Cu etch and Co Electroless Deposition for <10 nm IC metal interconnet

Along with the technology challenges of scaling MOSFETs in sub 10 nm IC chip fabrication, there is also challenges involving metal interconnects at deeper nodes. Cu damascene process is used for fabricating copper interconnects. But at deeper nodes, damascene process causes resistivity and reliability issues such as increased grain boundary and surface scattering. Here are the two latest innovation in metal interconnect technology:

1. Researchers at Japanese semiconductor equipment maker Tokyo Electron and Belgium based imec and have found a solution to replace damascene process with a direct Cu etch scheme for patterning Cu interconnects. They have presented a paper at IEEE International Interconnect Technology Conference (IITC) conference on May 18 – 21, 2015 at Grenoble, France.

Tokyo Electron said in its release: When scaling damascene Cu interconnects, reliability issues occur because the overall copper volume is reduced and interfaces become dominant. Direct Cu etch process keep the grain sizes larger and the electromigration performance is preserved by applying an in-situ SiN cap layer that protects the Cu wires from oxidation and serves as the Cu interface, explained by Tokyo Electron.

Cu Etch

Picture above: TEM section of copper etched lines encapsulated by SiN cap layer

2. At the same IEEE IITC conference, researchers from Lam Research and imec presented a novel bottom-up prefill technique for vias and contacts at using Electroless Deposition (ELD) of Cobalt (Co) technique resulting in void-free filling of via and contact holes.

The release from imec says "the high selectivity of the ELD process, at lower cost compared to Chemical Vapor Deposition (CVD), intrinsically ensures a good metal-to-metal interface and paves the way to void-free via filling and increased yield." "Trench fill yield and line resistance may also benefit from the de-coupling of line and via aspect ratios, permitting the design of each for optimum Resistance/Capacitance (RC). Therefore, Co prefill ELD has the potential to enable future scaling of advanced logic and memory technologies." further stated in the release.

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