HomeProductsProducts Details
Software
Date: 24-04-15

VLSI SoC layout design: FlexNoC phy interconnect IP reduce P&R iterations

Arteris is offering the new FlexNoC Physical interconnect IP for VLSI physical design of SoC chips. The layout friendly FlexNoC Physical IP is designed to reduce the timing issues experienced in the layout stage, reducing place and route (P&R) iterations and engineering change orders (ECOs).

Designed for using lesser wires, FlexNoC Physical interconnect IP offers fine-grained pipeline register placement nearly anywhere in the interconnect, and allows distributed IP placement.

FlexNoC Physical interconnect IP improves layout quality-of-results (QoR) and productivity by importing user-defined and production floorplans, automatically configuring pipelines to meet timing closure constraints, and separating the FlexNoC interconnect IP instances at a physical level so they can be routed separately from the rest of the SoC, explains Arteris.

The benefits of FlexNoC Physical IP as per Arteris includes:
Reduces or eliminates excessive P&R iterations – To resolve timing closure errors on long paths, SoC designers often have to iterate over multiple P&R runs, which can be very expensive. Optimizing the NoC interconnect IP early, prior to full SoC P&R, reduces the likelihood of timing closure issues during layout.
Eliminates trial-and-error timing closure with automated pipeline configuration – By analyzing the actual interconnect IP in the front-end design phase and automatically configuring pipeline stages as appropriate, chip teams hand over to the backend team a netlist that will close timing by design.
Optimizes Quality-of-Results (QoR) – SoC teams often over-design their chips in the front-end stage to avoid timing problems in the back-end. FlexNoC Physical IP intelligently estimates and predicts in the front-end phase where timing issues will occur in the back-end, allowing design teams to implement the minimum number of pipeline stages to achieve desired frequencies, while minimizing latencies and power consumption.
Separates the FlexNoC interconnect physical IP from the rest of the SoC – FlexNoC Physical offers features to separate the interconnect IP at the physical level the same way that it allows such isolation at the architectural level. Users can now generate interconnect floorplan outlines and treat the interconnect as a separate IP to be independently placed and routed by itself. Such a separation simplifies the job of the layout team.

“Using FlexNoC Physical delivers two valuable benefits: First, it allows SoC architects to visualize the physical implications of their topologies early in the design cycle, and second, it helps the RTL implementation team to automatically add pipelines for timing closure, cutting months off complex SoC development cycles” said K. Charles Janac, President and CEO of Arteris. “We are helping customers cut down place and route cycles by providing their layout teams better starting-point data.” comments Mike Demler, Senior Analyst, The Linley Group.

“Arteris is solving an important set of back-end problems with technology that works earlier in the SoC design flow,” said Mike Demler, Senior Analyst, at The Linley Group.

“FlexNoC Physical IP has the potential to significantly decrease timing issues experienced in the layout stage, reducing P&R iterations and engineering change orders (ECOs) and saving cost and schedule time.” says Bijan Kiani, Vice President of Marketing, Design Group, Synopsys.

“Arteris FlexNoC Physical has the promise to improve layout productivity by providing Synopsys tools, such as Design Compiler Graphical and IC Compiler II, with improved timing closure information and more accurate RTL data,” adds Bijan Kiani, Vice President of Marketing, Design Group at Synopsys. “We look forward to working with mutual customers to validate these propositions.”

Arteris FlexNoC Physical is available now for early access customers.

0 Comments
Default user
Related Products