Cadence Design Systems said its new VLSI design physical implementation place and route EDA software tool Innovus delivers 10 to 20 percent better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10nm node FinFET based VLSI chip design.
Innovus uses GigaPlace solver-based placement technology What Cadence describes as "that is slack-driven and topology-/pin access-/color-aware, enabling optimal pipeline placement, wirelength, utilization and PPA, and providing the best starting point for optimization"
Timing- and power-driven optimization feature in Innovus is multi-threaded and layer aware in bringing down dynamic and leakage power.
Innovus uses concurrent clock and datapath optimization including automated hybrid H-tree generation and slack-driven routing with track-aware timing optimization to take care of signal integrity early on and improves post-route correlation.
Simulataneous electrical and physical optimization for getting optimal PPA.
Features massively distributed parallel solution supporting implementation of design blocks with 10 million instances or larger.
Offers a common user interface (UI) across synthesis, implementation and signoff tools, and data-model and API integration with the Tempus Timing Signoff solution and Quantus QRC Extraction solution.
Full report on physical implementation tools in market in our next article some time in mid 2015.