Xilinx has launched new FPGA device "Virtex UltraScale VU440" having 4 million logic cells which is equivalent to 50 million equivalent ASIC gates, a highest gate count FPGA which has been shipped to its customers. Xilinx claims this new 28 nm chip delivers performance more than its competitors ( so mainly Altera) highest density FPGAs made using nodes smaller than 28 nm. How is it possible? It is more than Moore technology, basically stacking of wafers on a interposer, what is called as 2.5 D technology.
Xilinx' stacked silicon interconnect (SSI) technology stacks several (three or four) active FPGA dies side-by-side on a silicon interposer. Production qualified at the 28nm node, the SSI technology is built on TSMC's CoWoS (Chip-on-Wafer-on-Substrate) 3D IC process by integrating multiple components on a single device. Along with 5X more inter-die bandwidth and a unified clocking architecture across slice boundaries, UltraScale 3D IC devices deliver a virtual monolithic design experience for fast implementation and design closure.
With this VU440, high-density FPGA applications such as 400G MuxSAR, 400G Transponder and 400G MAC-to Interlaken bridge can be implemented in single chip.
The advantageous features in VU440 is, it has ASIC like architecture, where the gate utilisation rate is 90% by supporting advanced routing and ASIC like clocking. Basically interconnected bottlenecks are eliminated by optimising the critical paths. Virtex UltraScale VU440 features highest I/O count, logic block enhancement, high speed transceivers (48 x 16.3 Gb/s backplane-capable transceivers), and 89 Mb of block RAM.
Synopsys is leveraging this high-density FPGA in its HAPS FPGA-based prototyping development tool in offering higher capacity, increased performance and easier integration. This FPGA is billed as "ultimate prototyping device".
Xilinx has made a video demonstration of 10 ARM Cortex-A9 CPUs executing in a single Virtex UltraScale VU440.
The demo is available at
In a single monolithic FPGA device, speed and routing has some limitations. The solution to enhance data speed looks to be in multi-FPGA wafer stacking and interconnecting them through bus running below on the silicon interposer. But there is another better technology called silicon photonics, which Altera is focusing.
What's happeing in monolithic FPGA fabrication: Altera is using Intel's 14 nm process to make its most advanced and high-density FPGAs. 14 nm FPGAs from Intel's are expected to be shipped in the year 2015. Whereas Xilinx is utilising 16 nm foundry services from TSMC for its most advanced and high-density monolithic FPGA chips. Altera with the partnership with Intel looks to be ahead in launching the most high-density monolithic FPGA in the market. We got to see if Xilinx can shock the market by shipping a TSMC made 16 nm FPGA ahead of Intel made Altera 14nm FPGA.
What is more important to the customer in FPGA market is not the physical size of the chip and not even about whether its monolithic or 3-D. They would like to have a highest density single device FPGA which can run faster and is available at best cost. In that sense, more than Moore 3-D device VU440 from Xilinx may please the market (mainly SoC prototyping and communications/wireless) with its performance. But what about the cost? Xilinx has not disclosed whether it is offering its multi-stacked FPGA at a price less costlier than same gate count monolithic device.