eSilicon has added a new feature to its online soc design tool, where VLSI designers are provided with pre-loaded data for eSilicon memory compilers and I/O libraries, Generate dynamic, graphical analyses of power, performance and area (PPA) data View data graphically, in table/ Excel format.
Chip designers can build and download a complete chip memory subsystem generate and download IP front-end views and make changes over time and pay for the IP when ready for silicon tape out.
eSilicon offering IPs across multiple foundries and technologies which includes:
Memory compilers, including 28HPM TCAMs, four-port register files and two-port asynchronous register files
General-purpose I/O libraries from 16nm to 180nm
Specialty I/O libraries from 16nm to 180nm, including 1.8V/3.3V LVCMOS I/Os
"We wanted to simplify the comparison of results across multiple technologies, architectures and other characteristics and take the guesswork out of hitting PPA targets," said Lisa Minwell, eSilicon's senior director of IP product marketing. "This goes much, much deeper than IP portals that serve as IP catalogs. Using the IP MarketPlace environment, users can download front-end views, run simulations in their own environments, then come back to purchase the back-end views of the IP and I/Os that best fit their design."