Hybrid Memory Cube (HMC) 2.0 controller VLSI IP is available from Open Silicon for SoC designs where this IP already selected for application of high-speed networking equipment.
HMC specs developed by Hybrid Memory Cube Consortium (HMCC) leverages 3D packaging to connect multiple DRAM arrays to logic using through silicon vias (TSVs). The HMC 2.0 standard, recently ratified by the HMCC, specifies data rates up to 30 Gb/s.
“Our extensive background with both the integration of HMC IP and advanced design techniques is enabling a new generation of ASICs designed to address the growing bandwidth requirements of 100G and 400G networks, as well as high-performance computing,” said Hans Bouwmeester, Vice president of IP and Engineering Operations at Open-Silicon. “As a developer member of the HMCC, we are actively involved in defining the specification, and can deliver standards-compliant IP as soon as the standard is ratified.”
“Stacked DRAM and logic solutions, such as HMC 2.0, break through the memory bottleneck and deliver the performance and low-power needed by next-generation computing systems,” said Jim Handy, memory analyst with Objective Analysis. “Integration-ready interface solutions like Open-Silicon’s HMC controller IP should drive down the cost of deployment, and accelerate this transition.”
The soft macro implementation is designed to be compliant with both HMC v1.0 and the upcoming HMC v2.0 and seamlessly interface to third-party SerDes IP without the need for an additional PCS layer.