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Date: 16-09-14

28Gbps SerDes evaluation platform for 100G n/w chip design

VLSI design company Open-Silicon launched evaluation board with 28 nm test chip integrating 28Gbps Serializer/Deserializer (SerDes) for quickly designing silicon and systems for 100G networks. The test semiconductor chip features 28Gbps SerDes quad macro, using physical layer (PHY) IP from Semtech, and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications.

“Silicon-proven IP, such as the advanced 28Gbps SerDes PHY developed by Semtech, is central to our success as a leading ASIC solutions supplier,” said Taher Madraswala, president of Open-Silicon. “In selecting IP and IP partners, we take into account not only the overall functionality within the IP and its compatibility with other IP blocks, but also its interoperability within the ASIC tool flow and how reliably it can be manufactured in a high-volume process technology. The Semtech 28Gbps IP satisfies our stringent third-party IP requirements, and provides our ASIC customers with a reliable path to meeting the needs of 100G networks.”

“Having silicon results at this important 25G+ threshold is essential for customers to move forward with their plans to develop ASICs for the 100G network build-out,” said Kevin Walsh, director of worldwide marketing, Semtech Snowbush IP Group. “With Open-Silicon, we have a partner that can develop these complicated chips. We have worked closely with Open-Silicon and our joint customers on all aspects of design – from concept through to fully, manufactured and tested parts, and with that experience, we can now provide a fast track to the delivery of chips and systems for 100G networks and beyond.”

The Semtech SBMULTC2T28HPM28G PHY has an analog front end (AFE) that includes the transmit (Tx) and receive (Rx) path circuitry along with auxiliary blocks for clock generation, test and biasing. The Tx driver is a highly programmable block including multiple registers to allow adjustment of TX amplitude, de-emphasis and pre-emphasis. The PHY can be programmed to support multiple standards each with specific electrical performance characteristics. The area, power and latency have been optimized for use in SOCs, ASICs or ASSPs. A post-silicon tuning capability allows customers to adapt the performance of the PHY to different operating environments, explains Open Silicon.

“Until now, network systems manufacturers have had limited access to fully tested and proven third-party 28G SerDes IP – especially at the 28-nm node,” said Richard Wawrzyniak, IP analyst with Semico. “Evaluation platforms are key to enabling advanced network ASICs and SoCs that can handle growing bandwidth requirements in data centers, driven primarily by increased demand for cloud storage and Internet of Things applications.”

28G SerDes is suggested for ASIC and SoC deployment in high-data-rate, chip-to-chip and chip-to-module applications.

The 28-nm test chip has been packaged in a 19mm x 19mm, 324-ball high performance Low Temperature Co-Fired Ceramic (LTCC) Flipchip substrate. This package material was selected for its relatively wider trace characteristics, low loss tangent, and superior uniform via arrangements that minimize reflections in vertical transitions, says Open-Silicon .
The 28Gbps SerDes evaluation platform is expected to be available by the end of Q3 from Open-Silicon.

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