Accellera has unveiled backward-compatible UVM 1.2 standard for VLSI chip design verification. The new standard fixes lot of bugs. The new features include:
1. Messaging is now object-oriented enabling users to extend the built-in features
2. Sequences can automatically raise and drop objections for improved sequence control
3. The register layer can now control transaction order within bursts simplifying the verification of complex protocols
4. Reference implementation quality is enhanced with numerous bug fixes
Accellera is accepting VLSI design industry feedback and comments on these new standards up to 1st Oct 2014.
The multi-language working group of Accellera developing methods to develop and integrate VLSI IP written in different languages such as C and Specman. The release of specifications from this group are going to be sometime in the 3rd quarter of 2014.
Another working group at Accellera is adding SystemC support for UVM, including a full SystemC version of UVM, so that UVM support both SystemVerilog and SystemC. The spec are expected to be out by end of year 2014.
VLSI engineers at Bangalore can attend a dev conference by Accellera going to be held in Bangalore on 25-26 September 2014. The link for Bangalore event is: