In finFET based designs interconnects have become major cause of worry. VLSI design engineers can now look forward for faster interconnect parasitics extract/RC extractions tools supporting finFET based chip designs.
Cadence Design Systems says its enhanced Quantus RC extraction tool offers a 5X faster runtime compared to other in the market. TSMC has certified this tool for accuracy and FinFET functionality.
Enhanced Quantus has same fully certified libraries of its previous Cadence' QRC Extraction supporting different foundries. Cadence claims Quantus has tightest correlation to foundry golden data at TSMC compared to its competitors.
Quantus QRC Extraction supports both SoC and custom/analog chip design and includes a new foundry-certified integrated random-walk field solver called Quantus FS, which is again 5X faster and provides better throughput versus competing solutions, as per Cadence.
Cadence said Ricoh has cut its design flow parasitic extraction time in half for system-on-chip (SoC) designs, by using Cadence’s parasitic extraction solution for all large-scale, complex digital designs and mixed signal power management ICs for their mobile products.
Quantus QRC features a massively parallel architecture.
The competing RC extraction tools in the market include Synopsys StarRC, Mentor Graphics Calibre/xRC.
If you wish to learn how RC extracting can be speeded by using some special algorithms read the paper named:
"A Parasitic Extraction Method of VLSI Interconnects for Pre-Route at" at url: learn.tsinghua.edu.cn:8080/2003990088/papers/icccas10.pdf